TECHNICAL MANUAL.
// Comprehensive architecture breakdown, schematic references, and firmware logic for the BenchCore hardware platform.
Hardware Topology
The BenchCore system is built around a distributed processing and power regulation architecture. The primary logic is handled by an ESP32 WROOM-32 microcontroller operating on a FreeRTOS dual-core scheduler. Core 0 is strictly dedicated to critical safety loops and I2C/SPI sensor polling, while Core 1 handles MQTT cloud telemetry and WebSocket overhead.
Safety E-Stop Logic
Safety is enforced at the hardware level. The system utilizes a 10K NTC thermistor mechanically bonded to the primary XL4016 heatsink. If thermal limits (default 55°C) are breached, the hardware cuts power instantly via 5V logic relays, independent of the cloud connection.
MQTT Data Protocol
Telemetry is packaged into minimal JSON payloads and broadcast to a HiveMQ broker over WebSocket Secure (WSS) on port 8884. The payload size is kept strictly under 128 bytes to prevent heap fragmentation on the ESP32.
"v": 12.4,
"i": 1.85,
"w": 22.94,
"t": 42.1,
"st": 1 // 1=Online, 0=Cut
}